1. Technical Field
The present invention generally relates to methods of fabricating complementary metal-oxide-semiconductor (CMOS) devices, and more particularly to a method of fabricating a CMOS device having high dielectric constant (high-k) dielectric layer and metal gate electrode.
2. Description of the Related Art
With the continuous miniaturization of the dimensions of CMOS devices, traditional device film layers also encounter many challenges, new device materials for the development of very large scale integration (VLSI) will be an issue urgently needed to be resolved in the next few years. In recent years, the development of high-k dielectric layer and metal gate electrode has become one of the important researches in the semiconductor industry.
FIGS. 1A-1E are schematic sectional views illustrating a conventional method of fabricating a CMOS device including high-k dielectric layer and metal gate electrode.
First, referring to FIG. 1A, a semiconductor substrate 100 having a plurality of shallow trench isolation (STI) structures 102 formed therein defining an N-type MOS region 104 and a P-type MOS region 106 is provided. A silicon oxide layer 108 and a hafnium oxide (HfO2) layer 110 are sequentially formed over the substrate 100. The hafnium oxide layer 110 is comprised of a high-k dielectric material layer, the silicon oxide layer 108 serves as an interfacial layer (IL) between the substrate 100 and the hafnium oxide layer 110.
Subsequently, referring to FIG. 1B, a lanthanum oxide (LaO) layer 112 and an aluminum oxide (AlO) layer 114 are respectively formed over a portion of the hafnium oxide layer 110 at the N-type MOS region 104 and another portion of the hafnium oxide layer 110 at the P-type MOS region 106, for adjusting work functions of respective metal gate electrode.
Afterwards, referring to FIG. 1C, multiple gate stacked structures 116 are formed over the substrate 100 and respectively cover a part of the lanthanum oxide layer 112 and a part of the aluminum oxide layer 114. Each of the gate stacked structures 116 is comprised of a titanium nitride layer 118, a poly-silicon layer 120 and a hard mask layer 122 in an order from bottom to top.
Next, two wet etching steps are performed to form gate dielectric layers of the MOS devices.
Referring to FIG. 1D, a wet etching step 124 is performed; so that portions of the aluminum oxide layer 114 and the lanthanum oxide layer 112 uncovered by the gate stacked structures 116 are removed and thereby formed a patterned aluminum oxide layer 114a and a patterned lanthanum oxide layer 112a. The wet etching step 124 sequentially includes: loading the CMOS device into an etching machine, using a diluted hydrochloric acid (HCl) as etching solution, etching both the aluminum oxide layer 114 and the lanthanum oxide layer 112, cleaning device surfaces by using distilled water to remove residual etching solution, blow drying the device, and removing the device out from the etching machine.
After that, referring to FIG. 1E, another wet etching step 126 is performed, so that portions of the hafnium oxide layer 110 and the silicon oxide layer 108 uncovered by the gate stacked structures 116 are removed and thereby form a patterned hafnium oxide layer 110a and a patterned silicon oxide layer 108a. The wet etching step 126 sequentially includes: loading the CMOS device into the etching machine, using a diluted hydrofluoric acid (HF) as etching solution, etching the hafnium oxide layer 110 and the silicon oxide layer 108, cleaning device surfaces by using a distilled water to remove residual etching solution, blow drying the device, and removing the device out from the etching machine. Thus, the fabrication of the gate dielectric layers for the MOS devices is completed.
However, in the conventional method of fabricating the CMOS device, after etching the aluminum oxide layer 114, the lanthanum oxide layer 112, the hafnium oxide layer 110 and the silicon oxide layer 108, the polymers or other residues adhere on to the surface of the device, which would adversely influence the subsequent fabrication process and lead to poor yield and degrade the device performance.
Therefore, how to improve the above-mentioned issues and integrate the high-k dielectric layer and the metal gate electrode into a high yield and reliability of CMOS fabrication process will be one of important topics for the development of semiconductor device.